The present invention relates to frequency multipliers and, more particularly to a digital frequency multiplier for generating non-integer multiples of a reference frequency.
Various types of electronic circuits, such as integrated circuits (ICs), utilize/require clock signals or signals of different frequencies for operation of the different sections of circuitry or logic. In the case of ICs, many designs require several multiples (or sub-multiples) of a reference signal to clock blocks or sections of on-chip circuitry or logic. Rather than provide each different frequency reference signal to the IC from an external source, it is preferable to generate the different frequency signals on the IC utilizing a single input or reference signal. This eliminates the need to utilize an input/output (I/O) pin for every input signal.
If the frequencies of the required on-chip signals are greater than the frequency of the input/reference signal, often and typically a phase locked loop (PLL) configured as a frequency synthesizer is employed to generate the on-chip signals of the required frequencies. However, such a PLL is a relatively complex block of analog circuitry.
In FIG. 1, there is shown a block diagram representation of a prior art analog phase locked loop (PLL) circuit, generally designated 10, that is configured as an analog frequency synthesizer. In particular, the PLL 10 is operable to generate an output signal of a frequency that is a multiple of a frequency of an input signal. Operation of the prior art analog PLL 10 is described below.
An input signal fin of a particular frequency is input to a divide by M block 12 of appropriate analog circuitry, where M is any whole number. This results in a signal of fin/M frequency at an output of the divide by M block 12. The fin/M frequency signal is input into an analog phase detector 14. An output signal of the phase detector 14 is input into an analog low-pass filter 16. The output signal of the low-pass filter 16 is input to an analog voltage controlled oscillator (VCO) 18. An output signal of the VCO 18 is used as an input to drive a divide by N block 20 also characterized by appropriate analog where N is any whole number. An output signal of the divide by N block 20 is used to as an input to the phase detector 14 to complete a signal loop. As well, an output signal of the VCO 18 is input into an analog buffer 22. An output signal fout of the buffer 22 is the signal fin multiplied by N/M (i.e. fout=fin(N/M)).
The prior art analog PLL 10 as depicted in FIG. 1, while operable to generate an output signal having a frequency that is a fractional multiple of a frequency of an input signal is implemented by analog circuitry. Analog circuitry is not particularly compatible with digital circuitry such as in ICs. Additionally, analog circuitry takes up much needed space in an IC when so implemented. When an analog PLL is provided in an IC, such analog circuitry requires several dedicated I/O pins on the IC for a discrete loop filter and for the programmability of the M and N parameters. As well, typical digital gate array ICs require a separate discrete PLL chip or section for generating higher frequency clock signals from an input clock signal. An analog PLL will also draw a quiescent current.
The present invention is digital frequency multiplier that is operable to generate an output signal of a frequency that is a non-integer multiple of a frequency of an input/reference signal. The digital frequency multiplier is operable to synthesize an output signal having a frequency that is an over-unity, non-integer multiple of a frequency of an input signal.
In one form, the present invention is a digital frequency multiplier having frequency multiplying means, signal selection means, and control means. The frequency multiplying means is operable to receive an input signal of a given frequency and generate an intermediate signal of a frequency that is an integer multiple of the given frequency of the input signal. The signal selection means is in communication with the frequency multiplying means and is operable to receive the input signal and the intermediate signal and selectively output the input signal for a first predetermined period of time and the intermediate signal for a second predetermined period of time in response to a control signal to generate an output signal having a frequency that is a non-integer multiple of the given frequency of the input signal. The control means is in communication with the signal selection means and is operable to generate the control signal and provide the control signal to the signal selection means.
In another form, the present invention is a digital frequency multiplier having a frequency multiplier unit, a multiplexer, and a control signal generator. The frequency multiplier unit is operable to generate an intermediate signal having a frequency that is an integer multiple of a frequency of an input signal. The multiplexer has a first input in communication with the frequency multiplier unit to receive the intermediate signal, and a second input to receive the input signal. The multiplexer is configured to output the intermediate signal for a predetermined period of time in response to a control signal of a first state, and output the input signal for a predetermined period of time in response to a control signal of a second state, wherein the selective outputting of the intermediate signal and the input signal results in an output signal of a frequency that is a non-integer multiple of the input signal. The control signal generator is in communication with the multiplexer and is operable to generate the control signal of the first state and the control signal of the second state.
In yet another form, the present invention is a method of generating an output signal of a frequency that is a non-integer multiple of a frequency of an input signal. The method includes the step of: digitally generating an intermediate signal of a frequency that is an integer multiple of the frequency of the input signal; determining a first number of clock cycles of the input signal and a second number of clock cycles of the intermediate signal that, when combined, generate an output signal of a frequency that is the non-integer multiple of the frequency of the input signal; digitally generating a control signal indicative of the first number of clock cycles and the second number of clock cycles; and digitally selectively outputting the input signal for the first number of clock cycles and the intermediate signal for the second number of clock cycles in response to the control signal, whereby the selective outputting of the input signal and the intermediate signal results in an output signal of a frequency that is a non-integer multiple of the frequency of the input signal.